In many applications, data logic devices are utilized to transfer information from one point to the next, for example, these logic devices are utilized to connect devices on a network such as two processors. In other instances they may be utilized within a system to facilitate movement of data from one point within the system to another. Such devices utilize registers therewith to facilitate the movement and modification of data within such devices. Typically these registers interact with software for the necessary modification of the data.
The following sequence of software steps are necessary in the prior art to provide a new command in the register:
READ REGISTER PA1 SAVE A COPY OF THE REGISTER CONTENTS PA1 MASK OFF THE PART OF THE CONTENTS TO BE RETAINED PA1 MODIFY THE REGISTER CONTENTS PA1 COMBINE THE MODIFIED PART WITH THE RETAINED PART PA1 WRITE REGISTER
These steps take a significant amount of time and must be done a plurality of times when registers are connected in cascade.
Hence, there is along felt but unsatisfied need for a system which is less complex than prior art systems and at the same time, is able to provide a significant increase in the speed of execution of the register. In addition, the system should be one that will reduce the software complexity of the system. Finally, the system should be one that adds minimal cost to the hardware. The present invention addresses such a need.